Integrated circuits (IC's) typically include a large number of components, for example, transistors, resistors, capacitors, interconnection lines, etc. In accordance with each generation of technology nodes, each component of the IC may be formed as a respective structure on a chip (e.g., planer MOSFET's and FinFETs). In other words, each IC may have a respective surface configuration defined by its respective components. In general, a scanning electron microscopy (SEM) and an atomic force microscopy (AFM) are used to provide respective surface configurations of the plural components of the IC (i.e., a surface topography of the IC) so as to examine whether each of the components is properly fabricated during each of various fabrication stages.
The AFM typically relies on repulsive forces between a specimen substrate and an AFM probe tip to detect surface variations over the specimen substrate so as to reconstruct a respective topography of the specimen substrate using the surface variations. On the other hand, the SEM typically uses an electron beam to scan across a specimen substrate and one or more detectors to collect intensity variations of electrons scattered back from the specimen substrate so as to reconstruct a respective topography of the specimen substrate using the intensity variations of scattered-back electrons.
However, as the technology nodes continue to decrease in size, the SEM and AFM may each encounter various issues such as, for example, the AFM's low throughput (due to a limited number of AFM probe tips), possibilities to damage a specimen (due to the necessary contact of the AFM probe tip with the specimen), and the SEM's low throughput (due to a limited number of electron beams). Thus, conventional techniques to provide an IC's surface topography are not entirely satisfactory.